Exemplary embodiments relate to a method of operating a semiconductor memory device and, more particularly, to a method of operating a semiconductor memory device for storing data.
A NAND flash memory device is an example of a nonvolatile memory device. In order to increase the data storage capacity of the NAND flash memory device, data of 2 bits is stored in one memory cell. A memory cell has a threshold voltage varying according to the bit of data stored therein. That is, the threshold voltage of a memory cell is to be changed to store the data. The threshold voltage of a memory cell is changed by a program operation.
FIG. 1 is a circuit diagram illustrating the memory block of a NAND flash memory device.
Referring to FIG. 1, the NAND flash memory device includes a plurality of memory blocks. Each of the memory blocks includes a plurality of strings ST. The strings ST are coupled to respective bit lines BL0 to BLk and coupled to a common source CS. Each of the cell strings ST includes a drain select transistor coupled to a bit line (for example, the bit line BL1), a source select transistor coupled to the common source CS, and memory cells coupled in series between the drain select transistor and the source select transistor. The memory cells coupled in series constitute a memory string, and the drain select transistor becomes a cell string connection element for coupling the memory string to a bit line. The gates of the drain select transistors of the memory block are coupled to a drain select line DSL, and the gates of the source select transistors thereof are coupled to a source select line SSL. The gates of the memory cells are coupled to respective word lines WL0 to WLn. Meanwhile, the memory cells coupled to one word line (for example, WL0) constitute a page PB. One page PG may be divided into an even page, including the memory cells coupled to even-numbered bit lines, and an odd page including the memory cells coupled to odd-numbered bit lines. A program voltage and a program pass voltage for a program operation are supplied to the word lines WL0 to WLn. A ground voltage and a program inhibition voltage are selectively supplied to the bit lines BL0 to BLk according to data to be stored in corresponding memory cells. How the threshold voltages of memory cells are changed by a Least Significant Bit (hereinafter referred to as ‘LSB’) program operation and a Most Significant Bit (hereinafter referred to as ‘MSB’) program operation for storing data of 2 bits in a memory cell is described below.
FIGS. 2A and 2B are graphs illustrating a shift of the threshold voltages of memory cells according to a program operation.
Referring to FIG. 2A, prior to a program operation, all the memory cells are set to an erase state. That is, the threshold voltages of the memory cells drop to less than 0 V, and data stored in the memory cells is reset to ‘11’. Next, an LSB program operation is performed on memory cells selected from among the memory cells. Here, memory cells in which LSB data of ‘0’ is stored according to external inputted data are selected. The threshold voltages of the selected memory cells become higher than 0 V and the LSB data of the selected memory cells is changed from ‘1’ to ‘0’ by the LSB program operation. That is, the data stored in the selected memory cells are changed to ‘10’.
Referring to FIG. 2B, an MSB program operation is performed on memory cells selected from among all the memory cells. Here, memory cells in which MSB data of ‘0’ is stored according to external inputted data are selected. The threshold voltages of the selected memory cells are raised to three different levels PV1, PV2, and PV3 according to LSB data and MSB data of the selected memory cells by the MSB program operation. The MSB data of the memory cells is changed from ‘1’ to ‘0’. More particularly, the threshold voltages of memory cells having the LSB data maintained at ‘1’ and the MSB data changed (or stored) to ‘0’, from among the selected memory cells, rise up to the first program level PV1 higher than 0 V. The threshold voltages of memory cells having the LSB data changed (or stored) to ‘0’ and the MSB data maintained at ‘1’, from among the selected memory cells, rise up to the second program level PV2 higher than the first program level PV1. The threshold voltages of memory cells having both the LSB data and the MSB data changed (or stored) to ‘0’, from among the selected memory cells, rise up to the third program level PV3 higher than the second program level PV2.
For the LSB program operation or the MSB program operation, a program voltage is supplied to a selected word line, and a program pass voltage is supplied to unselected word lines. However, in order to raise the threshold voltages of the memory cells up to the three different program levels PV1 to PV3 in the MSB program operation, the program voltage is to be supplied to the selected word line several times. That is, a program pulse for raising the threshold voltages to the first program level PV1, a program pulse for raising the threshold voltages to the second program level PV2, and a program pulse for raising the threshold voltages to the third program level PV3 are to be supplied to the selected word line. As several program pulses are supplied in the single MSB program operation as described above, the program operation time may be increased.